Digital counter averaging system

ABSTRACT

An arrangement for averaging the count received from a bidirectional pulse source such as a measuring machine position transducer is disclosed in which a relatively small capacity auxiliary counter is utilized in conjunction with a main counter, and includes means for causing the incoming pulses in either direction to bypass the auxiliary counter and pass to the main counter whenever the auxiliary counter is full in the direction of the incoming pulse. The count in the auxiliary counter is periodically sampled with the samples taken at regular intervals and an update signal reflecting the direction of the average count being added to the main counter and subtracted from the auxiliary counter at regular intervals.

Unite States Patent 1191 Esch [ June 19, 1973 DIGITAL COUNTER AVERAGING SYSTEM [75] Inventor: RobertE.Esch,Dayton,Ohio

[73] Assignee: Kureha Kagalsu Kogyo Kabushiki Kaisha, Chuo-Ku,Tokyo, Japan [22] Filed: May 25, 1971 [21] Appl. No.: 146,712

Primary Examiner-Maynard R. Wilbur Assistant ExaminerJoseph M Thesz, Jr. Att0rneyJohn R. Benefiel and Plante, Hartz, Smith & Thompson [57] ABSTRACT An arrangement for averaging the count received from a bidirectional pulse source such as a measuring machine position transducer is disclosed in which a relatively small capacity auxiliary counter is utilized in conjunction with a main counter, and includes means for causing the incoming pulses in either direction to bypass the auxiliary counter and pass to the main counter whenever the auxiliary counter is full in the direction of the incoming pulse. The count in the auxiliary counter is periodically sampled with the samples taken [56] References Cited at regular intervals and an update signal reflecting the UNITED STATES PATENTS direction of the average count being added to the main 3,644,718 2/1972 Osborne et al. 235/92 EA counter and subtracted from the auxiliary counter at 3,57l,575 3/1971 Barr et al. 235/92 EV regular intervals 3,209,130 9/1965 Schmidt 235/92 PL 3,353,161 11/1967 Toscano 235 92 PL 7 Claims, 12 Drawing Flgul'es 3,500,023 3/1970 AI'IOWOOd et al. 235/92 PL 3,585,372 6/1971 Bell 6t 8] 235/92 MP s22 RJL M415 8 /0 /2 l 25 c'ou/vrse {fflflkl/IRD F .41. g

40x4 441?) 0/51; A Y TQMSDUCER 6/7 TIA/6 wuss- 1. Z Cau/VTER /6 OVER "75557 FLGW 40 .30

SAMPLE Ave/74667? fif-SET Puase 34 GE/YER/ITOR Patented June 19, 1973 5 Sheets-Sheet 5 BY WA /2 ATTORNEY FIG? 20 0 )6 lllllll-.. I I I ll H n? SC 5 Z I 3 F3 2 6% 1 M J... p m m 9 I9 4 4 w- 6 m a m p 48 T MI 5 m T mfl mw 6 F I. w 6 w 5 r4 0 5 4 W/ 3 5 a 0 T w, 9 4; I; w k 6 a a 7 T I M a R 6 71 W5 H 5 4 W. 2

Patented June 19, 1973 5 Shets-Sheet 5 Alf FL JL EJL 4 H HEJ l svnvN QWMQ INVENTOR ALH AL 11]] [EE[[ ROBERT E. ESCH BYM /& 8W

DIGITAL COUNTER AVERAGING SYSTEM BACKGROUND OF THE INVENTION Measuring machines which utilize position transducers producing a visual decimal display of the coordinate position of a probe are often subject to vibrations and other disturbances which render accurate reading of the decimal display difficult if not impossible. Such machines are usually designed to be insulated from such vibrations which typically originate from the operation of other machinery in the area, but none attenuate these sufficiently to solve the problem, in many installations.

In the case of such machines utilizing a transducer which generates bidirectional digital pulses, i.e., count up and count down pulses, combined with an up-down pulse counter to provide count corresponding to the probe position, the prior art approaches have usually involved combining averaging circuitry with a redesigned pulse counter to electronically average the count in the counter, which average is in turn displayed in the decimal display.

This approach has numerous disadvantages:

l. The circuitry involved to average the entire pulse count in the register necessarily is complex, potentially unreliable, and relatively expensive.

2. Since the averaging circuitry is connected between the counter and the pulse circuitry, typical designs will have a tendency to lose pulses arriving during averaging operations.

3. Since the decimal display in such designs typically reads only the average value, the true instantaneous count may lag considerably from that displayed. This is especially troublesome during rapid traversing of the probe, with the true pulse count varying rapidly.

4. Such an approach necessarily involves redesign of the counter and display electronics, hence making retrofitting of existing equipment difficult and expensive.

5. Typical averaging circuitry designs utilized in this approach will not correctly average asymmetric flutter patterns.

6. Since the pulse count contained in the counter is constantly shifting when the probe is subjected to vibration, the timing of the zero or offset reset pulse with respect to the phase of the vibration can introduce considerable errors in subsequent measurements.

Hence, it is an object of the present invention to provide a pulse count averaging system for a digital counter which substantially obviates these difficulties associated with the prior art approaches.

SUMMARY OF THE INVENTION This is accomplished according to the present invention by providing an auxiliary counter connected ahead of the main counter and decimal display. The auxiliary counter has a relatively small capacity relative to the main counter and pulses received from the pulse source are gated to the auxiliary counter until it is full in either direction, and thereafter pulses in that direction are gated directly to the main counter, as long as the auxiliary counter remains full in that direction.

The count contained in the auxiliary counter is sampled at regular intervals, these samples being periodically averaged and the average count then being subtracted from the auxiliary counter and added to the main counter.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the basic arrangement of the present invention.

FIG. 2 is a block diagram of a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of the synchronizer depicted in block form in FIG. 2.

FIG. 3a is a graphical representation of the operation of the synchronizer shown in FIG. 3.

FIG. 4 is a schematic representation ofa typical logic network depicted in block form in FIG. 2.

FIG. 5 is a schematic representation of the auxiliary counter depicted in block form in FIG. 2.

FIG. 6 is a schematic representation of the overflow detector depicted in block form in FIG. 2.

FIG. 7 is a schematic representation of the sampleraverager circuit shown in FIG. 2 in block form.

FIG. 8 is a schematic representation of the averager counter shown in block form in FIG. 2.

FIG. 9 is a schematic representation of the clock and sequencing circuitry shown in block form in FIG. 2.

FIGS. 10 and 11 are graphical representations of the sequencing of the various operations controlled by the clock and sequence circuitry.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description, specific embodiments will be described and certain terminology will be utilized for the sake of clarity, but it is to be understood that these are merely illustrative and the invention may be practiced in a variety of forms and embodiments.

Referring to the Figures, and particularly FIG. 1, a transducer 10 is represented which may be of a wellknown type as described in US. Pat. No. 2,886,718 which comprises a source of bidirectional signals which produces pulses over lines l2, 14 representative of increments of movement of the machine probe in the forward or reverse direction, respectively.

Pulses over lines 12 and 14 are connected to a gating network 16 which causes the pulses to proceed either directly to the main counter and display 18 via lines 20 and 22 or to the auxiliary counter 24 via lines 26, 28, depending on the state of the auxiliary counter 24.

Auxiliary counter 24 is an up-down relatively small capacity counter (i.e., four bit for example) with count up occurring with pulses on line 28 and count down occurring with pulses on line 26.

A sign flip-flop may be utilized in order to distinguish the count in the auxiliary counter as that corresponding to the forward or reverse direction.

In the event the auxiliary counter 24 contains a full count either corresponding to the forward or reverse direction, an overflow signal sent via line 30 controls the gating network I6, so that if a pulse in addition to the limited number able to be counted in the auxiliary counter 24 is received over lines 12 or 14 and, which pulse would add to the count of the full capacity counter 24, the pulse is then directed via line 20 or 22 directly to the main counter and display 18.

If the auxiliary counter 24 has not reached full capac ity, the pulse is then routed by the gating network 16 thereto, and not to the main counter and display 18 so that only the auxiliary counter receives pulses from the bidirectional signal source.

The count contained in the auxiliary counter 24 is periodieally sampled by the sampler-averager 32, and the average of the samples taken is computed at regular intervals. Many wellknown methods exist for performing this function, and a particular system utilizing a sampling register, accumulator, adder, and divider is disclosed in some detail infra.

The sample average is then transmitted to a pulse generator 34 which outputs a pulse count of the correct sign such that the sample average will be closer to zero after the next averaging cycle via lines 36, 38 so as to be added to that contained in the main counter and display 18, and at the same time subtracts this count from the auxiliary via lines 40, 42.

This pulse count may be either a single pulse, or the integer value of the sample average. In the first case the circuitry required is much simplified, but a relatively large number of averaging cycles may be required to reduce the auxiliary counter to zero. In the latter case, the system will settle in at most two averaging cycles, but the required circuitry would be more complex.

In operation, if the probe is being traversed by the operator, a steady train of pulses is received over either line 12 or 14, which pulses are routed to the auxiliary counter 24 over either line 26 or 28 until it becomes full in one or the other direction, at which point the overflow signal on line 30 causes rerouting of all additional pulses in the full direction by the gating network 16 directly to the main counter and display 18. Hence, the count displayed during traversing lags at a maximum only by the capacity of the auxiliary counter 24.

Upon cessation of the traversing operation, if vibrations or other disturbances are not present, the average of the samples will be read as the full capacity of the auxiliary counter 24, which average is added to the main counter and display 18 and subtracted from auxiliary counter 24 either at a rate of one or more pulses per averaging interval, or in its entirety in each averaging interval as described above so that after settling the true reading will be displayed by the main counter and the auxiliary counter will contain a zero count.

If vibrations do exist, a sampler-average 32 will determine the average count, and the pulse generator 34 will then add this value to the main counter 18 and subtract it from the auxiliary counter 24, until the average count in the auxiliary counter 24 during an averaging interval is zero. Thus, if the excursion of the vibrations corresponds to a pulse count within the capacity of the auxiliary counter 24, the main counter and display 18 will display the true average value of the probe position corresponding to the average value of the pulse count received over lines 12 and 14, while the auxiliary counter 18 will continuously receive every pulse from lines I2 and 14, with the sampler-averager 32 and pulse generator 34 ready to update the main counter and display I8 if the average count received in the auxiliary counter shifts from'zero.

Hence, since the true instantaneous count always is equal to the sum of the counts in the main counter and display 18, and the auxiliary counter 24, the main counter and display 18 reading can never lag from the true count by more than the capacity of the auxiliary counter 24.

It can also be appreciated that since the sampleraverager determines the average count by taking samples over an averaging interval, the true arithmetic average of flutter patterns which are asymmetric are correctly obtained.

By utilizing the approach of the present invention, another significant source or error mentioned above is minimized: In the typical system, the main counter must often be reset to zero or some offsetting value in order to begin measurements. If the resetting signal is applied at the time the system is subject to a vibration and if the signal arrives at the counter when the count is other than the average count corresponding to the vibration, the subsequent readings will be in error to the extent of the deviation from average. In the present system, if the reset signal from a signal source 40 sends a reset signal over line 42 to the main counter 18, and the system is vibrating, the main counter 18 will be unaffected by the phase of the reset signal and the vibrations.

In addition, it should also be appreciated that, as no redesign of the main counter or display is required, existing systems may be retrofitted merely by connecting the system of the present invention between the pulse source and the existing main counter.

Referring to FIG. 2, a block diagram of a preferred embodiment of the present invention is depicted. In this arrangement, the incoming pulses received over lines 12 and 14 as well as all of the sampling, averaging, and transmission of pulses from the averaging system to the main counter is synchronized and sequence controlled by a clock and control circuitry 48 to both eliminate the need for anti-coincidence circuitry and critical race conditions.

The incoming forward and reverse pulses on lines 12 and 14 are converted into logic levels by the synchronizer S4, with these logic levels being set in synchronism with the rest of the system operations by means of clock pulses received over line 56 from the clock and control circuitry 48 as will be discussed in more detail infra.

In this embodiment, rather than gating the incoming pulses from the transducer, the logic levels set by the synchronizer 54 controls, together with logic levels of the other components, the logic levels in a count directing logic network 58 which in turn controls the transmission of clock pulses received over lines 56, 60 from clock and sequencing circuitry 48 to the main counter and display 18, the auxiliary counter 24, and the average counter 64, to be described infra.

The auxiliary counter 24, which consists of a four bit bidirectional up-down counter together with an associ ated Sign flip-flop 64 is adapted to receive a limited number of pulses gated thereto by gating network 58 over lines 66 and 68 corresponding to forward and reverse pulses received on lines 12 and 14, until the auxiliary counter 24 reaches its full capacity in either the forward or reverse directions. At this point, an overflow detector 72 transmits a logic level signal to the gating network 58 via line A or 708 indicating full capacity in either the forward or reverse direction.

In this event, the gating network 58 directs all further clock pulses directed by logic levels in the synchronizer 50 which are set by pulses received over lines 12 and 14, in the direction of the full capacity, to be transmitted directly to the main counter and display 18 as in the basic system described supra.

The count and its sign contained in the auxiliary counter 24 is periodically sampled by the sampleraverager circuit 32 via lines 74 and 76 added into an accumulator and averaged at regular intervals, with the average and its sign being transferred into the average counter 62 and associated sign flip-flop 78 via lines 80, 82 after each averaging interval.

These sampling, adding, and transfer operations are controlled and synchronized by control pulses received from the clock and control circuitry 48 via lines 84, 86, 88 as will be described infra in more detail.

The average counter 61 includes an associated four input NOR gate (described infra) so that whenever the average is not zero a logic level input indicating such condition is transmitted to the gating network 58 via line 90, while the logic level of flip-flop 78 indicating the sign or direction of the average is transmitted thereto via line 92.

The gate network 58 in response to a non-zero logic level signal over line 92 allows clock pulses to be transmitted over the appropriate one of line pairs 20 and 22, 66 and 68, and 94 and 96 such that the average count is counted into the main register, and counted out of the auxiliary counter 24 and the average counter 62. That is, if the average counter indicates a non-zero average, and the sign flip-flop indicates the average is in the forward direction for example, the gate network 58 transmits forward pulses over line 20 to the main counter and display 18, and reverse pulses over lines 68 and 96 until the average counter 62 is counted down to zero, discontinuing the non-Zero logic level on line 90 to thus discontinue any further transmission of pulses. In a simlar manner, if the average count corresponds to the reverse direction, reverse pulses are fed into the main counter while forward pulses are fed into the auxiliary counter 28 and the average counter.

Thus the main counter 18 is updated with each average cycle and the average of the counts received by the auxiliary counter 24 is kept to zero, to thus display the correct arithmetric average count on the main counter and display 18.

In order to provide a better understanding of how to make and use the preferred embodiment of the present invention, a detailed description of each of the components indicated in the block diagram of FIG. 2 is here included.

The synchronizer 100 is depicted in detail in schematic form in FIG. 3.

The forward and reverse pulses carried over lines 12 and 14 are fed into the T input of a pair of flip-flops A, and A respectively, so that the trailing edge of the pulse received over line 12 or 14 sets Q high and 6 low of its respective A flip-flop.

The next clock pulse received over line 56 and fed into the T input of the respective B flip-flop B or B causes the high state of Q and the low state ofOof the A flip-flop to read over lines 94, 96, 98, and 100 into the J and K inputs of its associated B flip-flops, to set the respective B flip-flop Q high and 6 low, so that a high state is read over either line 52 or 54 and a low state over either 52 or 54.

The absence of a clock pulse (a clock pulse inverted at 102) is used to reset the A flip-flops if either of the B flip-flops are set by the l ogic combination of reading the level state of 52 and 54 into OR gate 104 via lines I06, 108 and feeding the output of the OR gate to AND gate 110 with the inverted absence of the clock pulse over line 112. This insures that the A flip-flops are read into the B flip-flops before they are reset.

The next clock pulse then resets the B flip-flop since the A flip-flops are then in the reset state.

Thus a pulse input on either line 12 or 14 results in a stateghange on either line 52 (and 33) or on line 54 (and 54) in synchronism with the clock pulses and of a duration of one clock cycle to provide proper functioning of the logic gating network.

FIG. 3a depicts this in graphical form.

Referring to FIG. 4, a schematic diagram of the logic network 58 is shown.

As described supra, the gating network 58 controls the transmission of clock pulses received over line 56 to the main counter 18 via lines 20, 22 to the auxiliary counter 24 via lines 66 and 68, and to the average counter 62 via lines 94, 96. In the particular embodiment disclosed, this is accomplished by inputing the clock pulses to one input of a series of AND gates 114, 116, 118, 120, 122, and 124 with the other input reading logic levels read on lines 126, 128, 130, 132, 134, and 136 respectively. Thus whenever the level states are as required as indicated on these lines, the AND gates cause a pulse to be transmitted therethrough to its respective line. Since some of the devices utilized require low going pulses as shown on lines 66, 68, and 94, 96, the pulses are inverted for this purpose.

The network of AND and OR gates to the left as viewed in FIG. 4 of the AND gates described is a typical hardware implementation of logic combinations which produce pulses of the proper type over the respective lines as follows:

Line 94 (Average Counter 62 Forward): A pulse is produced if the average counter 62 indicates a reverse average AND a reverse count is indicated on 54 OR no forward count in 52 AND no forward overflow indicated by the overflow detector 72 and line 52.

Line 96 (Average Counter Reverse): A pulse is produced if a forward average is indicated AND a forward count is on 52 OR no reverse count on 54 AND no reverse overflow is indicated by the overflow detector 72 and line 5 4.

Line 20 (Main Counter Forward): A pulse is produced if the line 96 is to receive a pulse, OR a forward count is indicated on line 52 AND a forward overflow condition is indicated by the overflow detector 72 and flip-flop 64.

Line 22 (Main Counter Reverse): A pulse is produced if line 94 is to receive a pulse, OR a reverse count is indicated on line 54 AND a reverse overflow is indicated by the overflow detector 72 and flip-flop 103.

Line 66 (Auxiliary Counter Forward): A pulse is produced if a forward count is indicated on line 52 AND line 20 is notla receive a pulse, OR no reverse count indicated on 54 AND line 94 is to receive a pulse.

Line 68 (Auxiliary Counter Reverse): A pulse is produced if a reverse count is indicated on line 54 AND line 22 is not to receive a pulse OR no forward count is indicated on line 5 AND line 96 is to receive a pulse.

The logic network shown is a NAND-NOR type of logic in order to conveniently provide the low going pulses required of the auxiliary and average counters 24 and 62.

It can readily be understood that these combinations will provide the overflow and average updating operations described above in reference to the block diagram of FIG. 2.

FIG. depicts the auxiliary counter 24 which is com prised of a four bit binary up-down counter 138 which receives count up pulses over the forward line 66 and count down pulses over the reverse line 68. Count up is done in a binary count while count down is done in a twos complement binary.

When the counter 138 is in the 0000 state and a pulse appears on line 68, the counter 138 generates a borrow pulse on line 140 while if it is in state 1111 and a pulse enters line 55 a carry pulse on line 19 is generated, both in the manner well known in the art.

The carry and borrow pulses are applied to the flipflop 64 so that line 152 is set to the high state whenever a pulse enters line 14 and set to the low state whenever a pulse enters line 140, so that a high state of line 152 (or low state of 1 5 2) indicates a positive or zero count in the counter 138 w hile a low state on line 152 (or a high state on line 152) indicates a negative count.

This logic level is used to generate the overflow detector signal and the average counts as described below.

The count contained in the auxiliary counter 24 is continuously monitored by the overflow detector 72 shown in FIG. 6 which consists of a four bit binary comparator 144 coupled with two NAND gates 146, 148. One side of the comparator is connected to the output of the counter via lines 76 and 150, while the other four bit input has the least significant bit connected to the logic one" and the three more significant bits connected to line 152 via line 74 and line 152 such that for a high logic level on line 152 indicating a zero or positive count in 138 the count is compared to binary 1 1 l 1 and for a low state on line 152 0001 indicating in twos complementary form a 15.

Thus when counter 138 is full in either direction, a high state is indicated on lines 154 and 156 to produce a low output on 70A if it is full in the positive sense (since 152 will then be high) or a low outputgnjOB when full in the down or negative sense (since 152 will then be high).

In all other conditions, the lines 70A and 70B will be 'high so that a low state on 70A indicates counter 138 is in an overflow state in the forward direction and a low state on line 708 indicates an overflow condition in the reverse direction. These signals are used as described in the logic gating network 58 to control the transmission of clock pulses.

FIG. 7 shows the sampler-averager 32 arrangement of the preferred embodiment in some detail. This arrangement includes a five bit shift register 160 which receives the count in the auxiliary counter in parallel fashion on inputs A A A and A and the sign on line T52 into input A., upon the application of a control pulse for circuit 48 received over line 162. This count is then added in serial fashion into an accumulator 164 which is composed of a pair of eight bit shift registers 166 and 168 coupled together to form a 16 bit shift register.

The shifting of the registers 160, 166, and 168 is controlled by pulses received from circuit 48 via line 170, while the adding is carried out by adder 172 which carries stored in a .l-K flip-flop 174.

In order to serially add the contents of the five-bit shift register into the sixteen bit accumulator 164 conveniently, the most significant flip-flop into which the sign has been entered via line 152 is connected to the serial input of the shift register 160 by line 176.-Thus,

the correct higher order digits are automatically added into the accumulator 164 in shifts over the fourth flipflop, i.e., zeros for forward binary counts and ones for reverse counts in twos complementary form in which form the reverse counts are received from the auxiliary counter 24 as described supra.

The sample register 160 is then reset by a signal received over line 178 from the clock and sequencing circuitry 48 and the cycle repeats itself.

At the end of an averaging cycle, 128 samples have been transferred successively into the sample register 160 and added into the accumulator 164 so that the shift registers 166 and 168 contain the sum of the 128 samples. The sample number 128 was chosen since it is a power 0f2 (2 and hence may be conveniently averaged by shifting the sum seven binary places to the right, which is accomplished in the present embodiment by reading the four flip-flops seven places to the left in the accumulator 164, over lines 80. The sign of the average may be read at one of the higher order bits to the left of the average flip-flops as on line 82, since the higher order bits will either be all ones indicating a twos complement binary number, and a reverse count or zeros indicating a binary positive count and a forward count.

Thus at the end of the averaging cycle, the average count read over line and its sign read over line 82 are entered into the average counter 62 and associated sign flip-flop 78 with the accumulator then cleared by a signal received from circuit 48 over line 80 to ready a new averaging cycle.

FIG. 8 shows the average counter 62 in some detail together with its associated sign flip-flop 78. The average counter 62 consists of a four-bit up-down counter 182 with its inputs connected to lines 80 and its outputs connected to a four input NOR gate 184 such that a logic one appears on line whenever no count is contained in counter 182, to thus provide the non-zero signal discussed supra.

Count up of the register occurs on pulses received over line 94 (forward) and count down occurs on pulses receiver over line 96 as described above.

A forced zero control signal received over line 185 from the clock and sequence circuitry is applied to NOR gate 184 during data transfer to prevent false reading by the logic network 58.

The sign fed into flip-flop 78 results in a high signal on line 28 and a low signal on E with a forward count in the average register and a low signal on 28 and a high signal on 28 with these signals being fed into the gating network 58 for control of the clock pulses as described above.

The clock and sequencing control circuitry 48 is shown in detail in FIG. 9 and includes a source of square wave pulses 186 divided by a flip-flop 188, with the frequency of the pulses on line 56 being selected to be well above the maximum frequency at which pulses will be received from the transducer in order to insure proper functioning of the logic network 58. In the preferred embodiment, the frequency of the source 186 was selected to be approximately 12 Mhz so that after division by a flip-flop 188 and AND gate 189 an 6 Mhz clock pulse runs on line 56.

The pulse train is further divided for control of the sampler-averager system by a one shot 190 shift register 192 combination.

The shift register shift input is connected to the 6 output of the shifted flip-flop 188 via line 194 so that it is shifted at a 6 Mhz rate.

The false output 4 of the one-shot 190 is connected to the serial input of the shift register 192, so that in the initial reset state, a one is fed into flip-flop of pin 3 of the shift register 190. The oneshot is immediately triggered by the 1 transition of the flip-flop of pin 3 via line 196 so that the false output 4 is caused to go low for the duration of the one shots period, precluding any further counts from being entered into the shift register 192 for the duration of the astable period. Thus, the one is propagated down the flip-flop and provides a sequenced timing signal at pins 5, 10, 12, and 13 for use in controlling the averaging circuitry.

After the one shot 190 again goes to its stable state, a one again appears at false output 4, and the cycle repeats. Variation of the RC circuit 191 values will cause a variation in the period of the one shot to thereby cause a variation in the time interval of the sampling, i.e., the sampling rate. This will allow adjustment thereof to a sampling rate suited to the frequency of the disturbances in a particular installation.

Three four-bit binary counters 198, 200, and 202 are used to count the shift and add operations of the sample and average circuit 32. The pulse from pin 30 of the shift register is transmitted via line 204 to line 170 to cause shifting of the shift registers as described infra, and with each such pulse a count is entered into counter 198 via line 206 to count the shifts. After 15 shifts, the next pulse sets all the bits of counter 198 to zero, which condition is detected by AND gate 208 to thus produce a high state on line 210 after 16 shifts, which when combined with the sequencing pulse from pin 5 in the AND gate 212 produces the inverted control pulse on line 178 to reset the sample register.

The sixteenth shift signal on line 210 is also combined in AND gate 214 with a sequence pulse from pin 10, and a 12 Mhz clock pulse from the source 186, to produce a low logic level on line 216, which is in turn combined with the Q output of flip-flop 188 via line 218 in AND gate 220 such that a high pulse is produced on line 162 when AND gate 220 is qualified. This pulse causes the transfer of data from the auxiliary counter to the sample register. it is selectively placed in time to insure a data transfer when the auxiliary counter is stable (not in process of changing state).

The sixteenth pulse also generates a carry pulse on line 222 to enter a count into counter 200, which is coupled to counter 202 via carry line 224. Thus every sixteen shifts indicating an add cycle is counted in coupled counters 200 and 202 until the 128 samples have been taken. The 128th sample causes the bit on pin 11 of counter 202 to become one, which causes resetting of all three counters as well as providing a logic input to AND gate 226 via line 228 and a control signal (forced zero) on line 185 (inverted by 230).

A sequence pulse from pin of shift register 192 is combined in AND gate 226 to provide the control signal to lines 86 and 88. This signal transfers the shifted average to the average counter register 62.

The pin 11 bit level also is combined in AND gate 232 with a sequence pulse from pin 12 of the shift registor to produce the clear signal C on line 180.

The clocking and control sequencing produced by the sequenced control signals is depicted graphically in FIGS. 8 and 9.

FIG. 8 shows the shift S, sample register reset R, and the transfer pulses T as they occur for each of the 128 add cycles, while FIG. 9 shows in detail the sequencing occurring at the end of the 128th add cycle.

While a specific embodiment incorporating the principle of the present invention has been described, the invention is of course susceptible of being utilized in many other different forms, and many alternative approaches to those taken in the specific embodiment could be taken within the spirit of the present invention.

For example, the use of a synchronizer and logic levels representing count pulses could be replaced by an arrangement in which a count pulse gating arrangement is combined with anti-coincidence circuits at the pulse summary junctions.

Similarly, the logic implementation of the gating function of either approach is of course susceptible of a great deal of variation in its hardware implementation as is well known in the art.

Also as described above, the average value of the samples taken of the count in the auxiliary counter may be added to the main register and taken from the auxiliary counter over a series of averaging cycles rather than in a single cycle as described in the specific embodiment.

The arithmetric operations of adding, dividing, etc., may of course be carried out by a great variety of computing techniques other than the specific technique disclosed as is apparent to those skilled in the art.

In addition, while the system is described as applied in connection with a measuring machine transducer, any counter in which bidirectional signals, i.e., in which up down counting is performed, may advantageously utilize the principle of the present invention.

What is claimed is:

l. A counter averaging arrangement for averaging the net count of signals received from a bidirectional signal source comprising:

bidirectional main counter means for counting said bidirectional signals;

bidirectional auxiliary counting means for counting said bidirectional signals; directing means for causing only said auxiliary counter means to receive and count said bidirectional signals until the capacity of said auxiliary counter means to count further signals in one or the other direction is reached, and causing additional source signals in said one or the other direc tion to be counted by said main counting means as long as said auxiliary counting means cannot count signals in said one or the other direction;

averager means for averaging the count contained in said auxiliary counter means over an interval of time;

signal generating means changing the count in said main counter means in the direction of said average count and changing the count in said auxiliary counter means in the opposite direction of said average count.

2. The arrangement of claim 1 wherein said signal generating means changes the count in said main and auxiliary counter means by said average count after each averaging interval.

3. The arrangement of claim 1 wherein said auxiliary counter means has a substantially smaller capacity than said main counter means.

rection or the other.

6. The arrangement of claim 1 wherein said main counter means includes a visual display of said count contained therein.

7. The arrangement of claim 1 wherein said signal source is a position transducer producing pulses corresponding to movement of a probe in a forward or reverse direction. 

1. A counter averaging arrangement for averaging the net count of signals received from a bidirectional signal source comprising: bidirectional main counter means for counting said bidirectional signals; bidirectional auxiliary counting means for counting said bidirectional signals; directing means for causing only said auxiliary counter means to receive and count said bidirectional signals until the capacity of said auxiliary counter means to count further signals in one or the other direction is reached, and causing additional source signals in said one or the other direction to be counted by said main counting means as long as said auxiliary counting means cannot count signals in said one or the other direction; averager means for averaging the count contained in said auxiliary counter means over an interval of time; signal generating means changing the count in said main counter means in the direction of said average count and changing the count in said auxiliary counter means in the opposite direction of said average count.
 2. The arrangement of claim 1 wherein said signal generating means changes the count in said main and auxiliary counter means by said average count after each averaging interval.
 3. The arrangement of claim 1 wherein said auxiliary counter means has a substantially smaller capacity than said main counter means.
 4. The arrangement of claim 1 wherein said averager means includes means for obtaining a plurality of successive samples of said count of said auxiliary counter means over said interval of time, and means for obtaining an average of said count samples.
 5. The arrangement of claim 1 wherein said directing means includes overflow detecting means producing signals indicating said incapacity of said auxiliary counter means to count further signals in said one direction or the other.
 6. The arrangement of claim 1 wherein said main counter means includes a visual display of said count contained therein.
 7. The arrangement of claim 1 wherein said signal source is a position transducer producing pulses corresponding to movement of a probe in a forward or reverse direction. 